1. Field of the Invention
This invention relates to digital logic, and more particularly to a new low-power architecture for digital logic that uses a switched inductor-capacitor (SLC) circuit to recycle charge while exhibiting the same logic behavior as standard digital logic.
2. Description of the Related Art
A logic gate is an idealized or physical device that implements a Boolean function. The logic gate performs a logical operation on one or more logical inputs, and produces a single logical output. Typical logic gates include “AND”, “OR”, “INVERTER”, “NAND”, “NOR”, “XOR” and “XNOR”. These logic gates are combined to design arbitrary digital logic circuits.
There are several logic families with different characteristics (power consumption, speed, cost, size) such as: RDL (resistor-diode logic), RTL (resistor-transistor logic), DTL (diode-transistor logic), TTL (transistor-transistor logic) and CMOS (complementary metal oxide semiconductor). Since the 1990s, most logic gates are made in CMOS technology (i.e. NMOS and PMOS transistors that function as switches).
Referring now to FIGS. 1a-1c, an inverter 10 (equivalent to “NOT” logic) receives a logical input A, inverts the logical state and produces an inverted output Q per truth table 11. A typical CMOS embodiment of inverter 10 includes series connected PMOS transistor 12 and NMOS transistor 14 between a high supply Vdd and a low supply Vss (e.g. ground potential). The logical input A is applied to the gates of both transistors. The logical output Q is provided at the series connection between the transistors. A logical input 0, turns PMOS transistor 12 on and NMOS transistor 14 off, which pulls the logical output Q to Vdd, a logical output 1. Conversely, a logical input 1, turns PMOS transistor 12 off and NMOS transistor 14 on, which pulls the logical output Q to Vss, a logical output 0. Each time the logical output changes state, one of the two transistors dissipates charge to the low supply (ground). If the top transistor is on, a path is formed from the supply to the output. If the bottom transistor is on, a path is formed to ground.
Referring now to FIGS. 2a-2c, a NAND gate 20 receives logical inputs A and B and performs the Boolean logic NAND (Not AND) function to produce logical output Y per truth table 21. A typical CMOS embodiment of NAND gate 20 includes a parallel connection of PMOS transistors 22 and 24 with a common drain connection to the high supply Vss. Their common source connection is connected to the top of a pair of series connected NMOS transistors 26 and 28 to the low supply Vss (ground). Logical inputs A and B are each applied to the gates of different ones of the NMOS and PMOS transistors, respectively. The logical output Y is produced at the top of the series connected NMOS transistors. If either logical input is 0, the logical output Y is pulled up to the high supply Vdd to logical output 1. If both logical inputs are 1, the parallel connected PMOS transistors are turned off and the series connected NMOS transistors are turned on pulling the logical output Y to the low supply Vss to logical output 0. Each time the logical output changes state, at least one of the transistors dissipates charge to the low supply (ground) or the output.
The demand for low power logic gates is acute. Often millions or even billions of logic gates are packaged to form a single integrated circuit. The density and switching speeds of logic gates is increasing at the same time that the use of battery operated wireless devices has soared.
Power dissipation in a CMOS based logic circuit is attributable to leakage current, short circuit current and switching energy. The leakage and short circuit current can be reduced to very low levels. Switching energy is more problematic. When a logic gate changes state, energy stored in the NMOS or PMOS transistors is dissipated. Extensive efforts have been made to reduce the switching energy in digital logic.
One approach to providing ultra-low power is to operate the digital logic gates in the subthreshold region. The incentive of operating the circuit in subthreshold mode is to be able to exploit the subthreshold leakage current as the operating drive current. This approach only allows quadratic reductions in power and sacrifices switching speed. Subthreshold logic consumes about 20 fj to 50 fj per switching operation. See Hendrawan Soeleman and Kaushik Roy “Ultra-Low Power Digital Subthreshold Logic Circuits” ISPLED, San Diego, Calif., 1999.
Asynchronous logic reduces power consumption but again only by a polynomical factor. See Marr, Bo, et al. “Scaling Energy Per Operation via an Asynchronous Pipeline.” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 21.1 (2013): 147-151.
Janusz A. Starzyk and Haibe He, “A Novel Low Power Logic Circuit Design Scheme”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 54, No. 2, February 2007 is based on energy exchange in a Switched Inductor-Capacitor (SLC) circuit. Each time the logic circuit is switched, and the load capacitor discharged, instead of dissipating the energy to ground the energy is stored in the magnetic field of the inductor. As shown in FIG. 1 of this IEEE paper, a basic logic gate structure consists of a switch control unit (SCU) with two control signals s1 and s2 and two energy storage elements—inductor (L) and load capacitor C. Inside the SCU, there are four switches controlled by two-phase control signals CS1 and CS2, which control switches s1 and s2, respectively. This circuit works as an inverter. Based on the control signals CS1 and CS2 value, this circuit will have four phases of operation illustrated in FIG. 3 of this IEEE paper. While CS1 is an arbitrary input signal, CS2 is the CS1 signal shifted by T/4. Various logic gates can be built using the described energy exchange and storage mechanism.